Referring to FIG. 1, a flash memory cell 100 of a flash memory device includes a tunnel dielectric structure 102 typically comprised of silicon dioxide (SiO2) or nitrided oxide as known to one of ordinary skill in the art of integrated circuit fabrication. The tunnel dielectric structure 102 is disposed on a semiconductor substrate or a p-well 103. In addition, a floating gate structure 104, comprised of a conductive material such as polysilicon for example, is disposed over the tunnel dielectric structure 102. A control dielectric structure 106, typically comprised of silicon dioxide (SiO2) and silicon nitride (Si3N4), such as an ONO (oxide-nitride-oxide) structure for example, is disposed over the floating gate structure 104. A control gate structure 108, comprised of a conductive material, is disposed over the control dielectric structure 106.
A drain bit-line junction 110 that is doped with a junction dopant, such as arsenic (As) or phosphorous (P) for example, is formed within an active device area 112 of the semiconductor substrate or p-well 103 toward a left sidewall of the floating gate structure 104 in FIG. 1. A source bit-line junction 114 that is doped with the junction dopant is formed within the active device area 112 of the semiconductor substrate or p-well 103 toward a right sidewall of the floating gate structure 104 of FIG. 1.
During the program or erase operations of the flash memory cell 100 of FIG. 1, charge carriers are injected into or tunneled out of the floating gate structure 104. Such variation of the amount of charge carriers within the floating gate structure 104 alters the threshold voltage of the flash memory cell 100, as known to one of ordinary skill in the art of flash memory technology. For example, when electrons are the charge carriers that are injected into the floating gate structure 104, the threshold voltage increases. Alternatively, when electrons are the charge carriers that are tunneled out of the floating gate structure 104, the threshold voltage decreases. These two conditions are used as the two states for storing digital information within the flash memory cell 100, as known to one of ordinary skill in the art of flash memory technology.
For example, during programming of the flash memory cell 100 that is an N-channel flash memory cell, electrons are injected into the floating gate structure 104 to increase the threshold voltage of the flash memory cell 100. Alternatively, during erasing of the N-channel flash memory cell 100, electrons are pulled out of the floating gate structure 104 to the substrate or p-well 103 to decrease the threshold voltage of the flash memory cell 100.
FIG. 2 illustrates a circuit diagram representation of the flash memory cell 100 of FIG. 1 including a control gate terminal 120 coupled to the control gate structure 108, a drain terminal 122 coupled to the drain bit-line junction 110, a source terminal 124 coupled to the source bit-line junction 114, and a substrate or p-well terminal 126 coupled to the substrate or p-well 103. FIG. 3 illustrates a flash memory device 130 comprised of an array of flash memory cells, as known to one of ordinary skill in the art of flash memory technology.
Referring to FIG. 3, the array of flash memory cells 130 includes rows and columns of flash memory cells with each flash memory cell having similar structure to the flash memory cell 100 of FIGS. 1 and 2. In the array of flash memory cells 130, the control gate terminals of all flash memory cells in a row of the array are coupled together to form a respective word-line for that row. In FIG. 3, the control gate terminals of all flash memory cells in the first, second, third, and fourth rows are coupled together to form the first, second, third, and fourth word-lines 132, 134, 136, and 138, respectively.
In addition, the drain terminals of all flash memory cells in a column are coupled together to form a respective bit-line for that column. In FIG. 3, the drain terminals of all flash memory cells in the first, second, third, fourth, fifth, sixth, seventh, eighth, and ninth columns are coupled together to form first, second, third, fourth, fifth, sixth, seventh, eighth, and ninth bit-lines 142, 144, 146, 148, 150, 152, 154, 156, and 158, respectively. An array of flash memory cells for a flash memory device typically has more numerous rows and columns, but four rows and nine columns are illustrated in FIG. 3 for simplicity and clarity of illustration.
Further referring to FIG. 3, the source terminal of all flash memory cells of the array 130 are coupled together to a source voltage VSS. In addition, the substrate or p-well terminals for all flash memory cells of the array 130 are coupled together to a substrate voltage VSUB (not shown in FIG. 3 for clarity of illustration). The source voltage VSS and the substrate voltage VSUB may be ground for example.
In FIG. 3, VSS lines, including first, second, and third VSS lines, 162, 164, and 166 are periodically situated after a predetermined number of bit-lines. In FIG. 3 for example, the first, second, and third VSS lines, 162, 164, and 166 are each situated after four bit-lines. The source terminal of all flash memory-cells of the array 130 are coupled to the VSS lines, 162, 164, and 166. A plurality of the VSS lines, 162, 164, and 166 are interspersed between the bit-lines of the array 130 for minimizing resistance at the source terminal of all flash memory cells of the array 130.
Referring to FIG. 3, when an example flash memory cell 170 of the array 130 comprised of N-channel cells is programmed, approximately 10 Volts is applied to the word-line 136 for the flash memory cell 170, approximately 5.5 Volts is applied to the bit-line 144 for the flash memory cell 170, and the source and substrate terminals for the flash memory cell 170 are typically grounded. With such voltages applied, electrons are injected into the floating gate of the flash memory cell 170 to raise the threshold voltage of the flash memory cell 170.
During programming of the example flash memory cell 170, such electron injection may disadvantageously affect the threshold voltage of the neighboring flash memory cells 172, 174, 176, and 178. Such undesirable effect on the threshold voltage of the adjacent flash memory cells 172, 174, 176, and 178 is via FG—FG (floating gate to floating gate) capacitive coupling during such electron injection.
Adjacent flash memory cells 172 and 174 share the same word-line 136 with the flash memory cell 170. FIG. 5 illustrates a cross-sectional view of the flash memory cell 170 and one of the adjacent flash memory cells 172 and 174 sharing the same word-line 136. In FIG. 5, if the tunnel dielectric 102, the floating gate 104, and the control dielectric 106 to the left are for the flash memory cell 170, then a tunnel dielectric 202, a floating gate 204, and a control dielectric 206 to the right are for one of the adjacent flash memory cells 172 or 174.
A control gate 208 is continuous across the flash memory cells 170 and 172 for forming the common word-line 136 for a row of flash memory cells. The inter-level dielectric 194 surrounds the gate structures of such adjacent flash memory cells in FIG. 5. Shallow trench isolation structures 151, 153, and 155 formed in the substrate 103 define the active device areas of the flash memory cells in FIG. 5. The two floating gates 104 and 204 of the adjacent flash memory cells of FIG. 5 are separated by a distance 219.
Similarly, FIG. 4 illustrates a cross-sectional view of the flash memory cell 170 and the adjacent flash memory cells 176 and 178 sharing the same bit-line 144. In FIG. 4, the tunnel dielectric 102, the floating gate 104, the control dielectric 106, and the control gate 108 are for the flash memory cell 170. Similarly, the tunnel dielectric 201, the floating gate 203, the control dielectric 205, and the control gate 207 are for the flash memory cell 176. In addition, the tunnel dielectric 209, the floating gate 210, the control dielectric 211, and the control gate 212 are for the flash memory cell 178.
Furthermore, the flash memory cell 176 has a drain bit line junction 213 and a source line junction 214, the flash memory cell 170 has the source line junction 214 and a drain bit line junction 215, and the flash memory cell 178 has the drain bit line junction 215 and a source line junction 216. The inter-level dielectric 194 surrounds the gate structures of the flash memory cells in FIG. 4. The flash memory cells 176 and 170 share the common source line junction 214, and the flash memory cells 170 and 178 share the common drain bit line junction 215. Such source and drain line junctions 214 and 215 are shared for minimizing the area occupied by the flash memory cells of the array 130.
Typically, an example flash memory cell 170 of the array 130 has one neighboring flash memory cell 176 sharing a common source line junction 214 and has another neighboring flash memory cell 178 sharing a common drain bit line junction 215. The two floating gates 203 and 104 of the adjacent flash memory cells 176 and 170 sharing the common source line junction 214 are separated by a distance 217. Similarly, the two floating gates 210 and 104 of the adjacent flash memory cells 178 and 170 sharing the common drain bit line junction 215 are separated by a distance 218. The distance 218 over the common drain bit line junction 215 is typically much larger than the distance 217 over the common source line junction 214 because a contact is formed on the common drain bit line junction 214.
Referring to FIGS. 3, 4, and 5, with constant advancement of flash memory technology, the structures of flash memory cells of the array 130 are formed to be smaller and denser. Thus, the distances 217, 218, and 219 between the floating gates of adjacent flash memory cells in the array 130 is constantly decreasing with advancement of flash memory technology. With such smaller distances 217, 218, and 219, especially the distances 217 and 219, between the floating gates of adjacent flash memory cells, FG—FG coupling becomes more prevalent.
For example, referring to FIGS. 4 and 5, during programming of the flash memory cell 170, electrons are injected into the floating gate 104. However, with the smaller distances 217 and 219, the electrons injected into floating gate 104 affect the threshold voltage of the adjacent flash memory cells via FG—FG capacitive coupling.
Typically, the common drain bit line junction 215 is relatively large for forming a contact thereon. Thus, the distance 218 is relatively large, and FG—FG coupling between the floating gates 104 and 210 is typically negligible as a result. With the smaller distances 217 or 219, the capacitance between adjacent floating gates 104 and 203 or 204 is larger causing the threshold voltage of the adjacent flash memory cells to undesirably increase via FG—FG capacitive coupling.
Unfortunately, the prior art does not compensate for such undesired FG—FG coupling during programming of a flash memory device. FIG. 6 shows a flow-chart of steps for programming a group of flash memory cells in a page. The whole array 130 for a flash memory device is divided into pages, and the steps of FIG. 6 are performed for programming a group of flash memory cells within a page at a time.
Typically, each flash memory cell of an array is first erased to an initial lower threshold voltage such as 2 Volts for example. Referring to FIG. 6, the address of each flash memory cell of a group of flash memory cells to be programmed is indicated (step 222 of FIG. 6). A program verify step is performed to determine if the threshold voltage of a flash memory cell of the group to be programmed has not attained the program verify level and thus does not pass program verify (step 224 of FIG. 6).
If all flash memory cells of the group to be programmed pass program verify (step 226 of FIG. 6), then programming for the group ends. On the other hand, if a flash memory cell of the group does not pass program verify (step 226 of FIG. 6), a programming pulse is generated for the flash memory cell of the group not passing program verify (step 228 of FIG. 6). During such a programming pulse, programming voltages are applied on the respective word-line and bit-line for the flash memory cell of the group not passing program verify in steps 224 and 226 of FIG. 6. Such programming voltages raise the threshold voltage of such a flash memory cell, and steps 224, 226, and 228 are repeated until all flash memory cells of the group pass program verify at step 226.
The prior art steps of FIG. 6 for programming do not compensate for FG—FG coupling between adjacent flash memory cells. However, when an adjacent flash memory cell sharing a same word-line or bit-line is programmed to the final threshold voltage, such as 5 Volts for example, FG—FG coupling may cause the threshold voltage of an adjacent flash memory cell to change by hundreds of milli-volts.
For example, referring to FIG. 3, assume that flash memory cells 170, 172, 174, 176, and 178 are part of one page of the flash memory device 130. In addition, assume that any flash memory cell of the array 130 is desired to be programmed to the final threshold voltage of 5 Volts for example. Furthermore, assume that in an example programming algorithm, the flash memory cells 170, 172, 174, 176, and 178 are programmed sequentially in that order. Thus, the flash memory cell 170 is first programmed to the final threshold voltage of 5.0 Volts, and then the flash memory cell 172 is programmed to the final threshold voltage of 5.0 Volts, and so on sequentially through the flash memory cell 178.
Referring to FIGS. 4 and 5, the distance 219 between the floating gates 104 and 204 for adjacent flash memory cells sharing a same word-line is typically low enough such that FG—FG coupling between such cells is significant during programming. In addition, the distance 217 between the floating gates 203 and 104 for adjacent flash memory cells 176 and 170 sharing a common source line 214 is typically low enough such that FG—FG coupling between such cells is significant during programming. On the other hand, the distance 218 between floating gates 210 and 104 for adjacent flash memory cells 178 and 170 sharing a common drain bit line 215 is relatively large such that FG—FG coupling between such cells is negligible.
Referring back to the example of the five flash memory cells 170, 172, 174, 176, and 178 to be programmed, assume that when a flash memory cell is programmed to the final threshold voltage of 5 Volts, the effect on the threshold voltage of an adjacent flash memory cell sharing a same word-line is 300 milli-volts. In addition, assume that the effect on the threshold voltage of an adjacent flash memory cell sharing a common source line is 400 milli-volts.
First, assume that the flash memory cell 170 is programmed to have the final threshold voltage of 5 Volts, according to the steps of FIG. 6. Then, if any of the adjacent flash memory cells 172, 174, 176, 178 of the same page is subsequently programmed to have the final threshold voltage of 5 Volts, the threshold voltage of the flash memory cell 170 undesirably increases from FG—FG coupling.
Assume the worst case scenario of all of the adjacent flash memory cells 172, 174, 176, 178 being part of the group to be subsequently programmed for the page. In that case, when the adjacent flash memory cells 172 and 174 sharing the same word-line are programmed to the final threshold voltage of 5 Volts, the threshold voltage of the flash memory cell 170 increases by a total of 600 milli-volts to 5.6 Volts. Additionally, when the adjacent flash memory cells 176 and 178 sharing the same bit-line are programmed to the final threshold voltage of 5 Volts, the threshold voltage of the flash memory cell 170 increases by a total of 400 milli-volts to 6.0 Volts. In this manner, the flash memory cell 170 has an undesired increase of 1.0 Volts to the final threshold voltage after programming the group of flash memory cells 170, 172, 174, 176, and 178 according to the prior art steps of FIG. 6.
Note that FG—FG coupling affects the threshold voltage of an adjacent flash memory when a given flash memory cell is programmed subsequently after that adjacent flash memory cell has already been programmed. On the other hand, if the adjacent flash memory cell is programmed after the given flash memory cell has already been programmed, the disturbance to the threshold voltage of the adjacent flash memory cell from FG—FG coupling is taken into account during program verify such that the effect of FG—FG coupling is not apparent for the adjacent flash memory cell. Thus, in the example of the flash memory cells 172, 174, 176, and 178 being programmed subsequent to the flash memory cell 170, the flash memory cells 172, 174, 176, and 178 attain a threshold voltage of substantially 5.0 Volts after the steps of FIG. 6.
Furthermore, in multi-level flash memory devices, different flash memory cells of the array 130 are programmed to different threshold voltages. Such flash memory cells of a multi-level flash memory device are used for storing multi-bit information, as known to one of ordinary skill in the art of flash memory technology. For example, referring to FIG. 3, assume that the flash memory cell 170 is to be programmed to have a threshold voltage of 3 Volts while the flash memory cell 174 is to be programmed to have a threshold voltage of 5 Volts.
In that case, referring to FIGS. 3 and 6, the loop of steps 224, 226, and 228 are repeated until the flash memory cell 170 attains a threshold voltage of 3 Volts and until the flash memory cell 174 attains a threshold voltage of 5 Volts. There are numerous algorithms for programming the flash memory cells 170 and 174 to the different threshold voltages, as known to one of ordinary skill in the art of multi-level flash memory devices. However, typically, both of the flash memory cells 170 and 174 are programmed to have a threshold voltage of 3 Volts, and then the threshold voltage of the flash memory cell 174 is additionally raised to 5 Volts. During programming for the additional 2 Volts change in the threshold voltage of the flash memory cell 174, FG—FG coupling between flash memory cells 170 and 174 may undesirably raise the threshold voltage of the flash memory cell 170 to 3.2 Volts.
Such undesired change in the threshold voltage of a flash memory cells from FG—FG coupling may result in error during reading of data from the flash memory cell. Thus, a mechanism is desired for compensating for such FG—FG coupling during programming of the flash memory device.